perf: Enable signed requantized max pooling with differing qinfo#1286
perf: Enable signed requantized max pooling with differing qinfo#1286
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Is this really a fix? Sounds like a |
gunes-arm
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I've made one comment re. the commit title (and please change the Pr, too)
Also, this one:
Keep AVG pooling unchanged and leave SME2 on the existing guarded path.
I think this should be SME, not SME2. Nit pick :)
As long as someone looks at the assembly code, I'm ok with the rest of the changes and the tests.
Enable QASYMM8_SIGNED NHWC MAX pooling with differing input/output quantization info in the asm wrapper. Fix the A64/SVE2/SME signed requantized max pooling kernels to apply input and output offsets correctly, and add NEON pooling validation and execution coverage for the supported signed padded MAX cases. Keep AVG pooling unchanged and leave SME on the existing guarded path. Measured uplift vs generic fallback: - Neon™: 6.28x (112x112x64), 6.64x (56x56x256) - SVE: 6.48x, 7.22x - SME: 4.14x, 9.15x Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com> Change-Id: I6105404638ce11e32ec3a1275eea26e0b795b98a
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Addressed in the latest patchset. |
Enable QASYMM8_SIGNED NHWC MAX pooling with differing input/output quantization info in the asm wrapper.
Fix the A64/SVE2/SME signed requantized max pooling kernels to apply input and output offsets correctly, and add NEON pooling validation and execution coverage for the supported signed padded MAX cases.
Keep AVG pooling unchanged and leave SME2 on the existing guarded path.
Change-Id: I6105404638ce11e32ec3a1275eea26e0b795b98a